VideoCore QPU Pipeline

As a followup to the last post, I've taken a closer look at the Quad Processor Unit that executes shaders on the VideoCore GPU. Although it superficially looks like a CPU, there are some important fundamental differences, and the reasons for them are interesting.

Evaluating Instruction Set Tradeoffs Quantitatively

While a great deal of research is devoted to CPU performance at the microarchitectural level, I haven't found much rigorous analysis of performance tradeoffs inherent to the design of instruction sets themselves. And while it's instructive to examine existing processor instruct sets, without knowing what alternative options were considered, what the tradeoffs where, and ultimately why decisions were made, a lot of important information is missing. For example, one key insight in early research into RISC performance came from analysis of instruction frequencies in common CISC programs.  It would found that the more complex instructions were used substantially less frequently than simpler ones.

I've decided to explore some of the decisions I made in my own processor design (https://github.com/jbush001/GPGPU) empirically.  This processor is targeted by a C++ compiler based on the LLVM toolchain. The beauty of LLVM is that backend code generation is heavily data driven based on templated patterns specified in configuration files processed by a tool called "TableGen." This makes it relatively easy to quickly make substantial changes to code generation.  My experimental methodology is to disable usage of certain instruction set features, and measure the resulting performance of a compiled program.